Semiconductor devices are commonly found in modern electronic products. Semiconductor devices vary in the number and density of electrical components. Discrete semiconductor devices generally contain one type of electrical component, e.g., light emitting diode (LED), small signal transistor, resistor, capacitor, inductor, and power metal oxide semiconductor field effect transistor (MOSFET). Integrated semiconductor devices typically contain hundreds to millions of electrical components. Examples of integrated semiconductor devices include microcontrollers, microprocessors, charged-coupled devices (CCDs), solar cells, and digital micro-mirror devices (DMDs).
Semiconductor devices perform a wide range of functions, such as high-speed calculations, transmitting and receiving electromagnetic signals, controlling electronic devices, transforming sunlight to electricity, and creating visual projections for television displays. Semiconductor devices are found in the fields of entertainment, communications, power conversion, networks, computers, and consumer products. Semiconductor devices are also found in military applications, aviation, automotive, industrial controllers, and office equipment.
Semiconductor devices exploit the electrical properties of semiconductor materials. The atomic structure of semiconductor material allows its electrical conductivity to be manipulated by the application of an electric field or base current or through the process of doping. Doping introduces impurities into the semiconductor material to manipulate and control the conductivity of the semiconductor device.
A semiconductor device contains active and passive electrical structures. Active structures, including bipolar and field effect transistors, control the flow of electrical current. By varying levels of doping and application of an electric field or base current, the transistor either promotes or restricts the flow of electrical current. Passive structures, including resistors, capacitors, and inductors, create a relationship between voltage and current necessary to perform a variety of electrical functions. The passive and active structures are electrically connected to form circuits, which enable the semiconductor device to perform high-speed calculations and other useful functions.
Semiconductor devices are generally manufactured using two complex manufacturing processes, i.e., front-end manufacturing, and back-end manufacturing, each involving potentially hundreds of steps. Front-end manufacturing involves the formation of a plurality of die on the surface of a semiconductor wafer. Each die is typically identical and contains circuits formed by electrically connecting active and passive components. Back-end manufacturing involves singulating individual die from the finished wafer and packaging the die to provide structural support and environmental isolation.
One goal of semiconductor manufacturing is to produce smaller semiconductor devices. Smaller devices typically consume less power, have higher performance, and can be produced more efficiently. In addition, smaller semiconductor devices have a smaller footprint, which is desirable for smaller end products. A smaller die size may be achieved by improvements in the front-end process resulting in die with smaller, higher density active and passive components. Back-end processes may result in semiconductor device packages with a smaller footprint by improvements in electrical interconnection and packaging materials.
The electrical interconnection in a fan-out wafer level chip scale package (FO-WLCSP) containing semiconductor die stacked on multiple levels can be accomplished with conductive through silicon vias (TSV), through hole vias (THV), and Cu-plated conductive pillars. Vias are formed in silicon or organic material around the die using mechanical drilling, laser drilling, or deep reactive ion etching (DRIE). The vias are filled with conductive material, for example by copper deposition using an electroplating process, to form the conductive TSVs and THVs. The TSVs and THVs further connect through build-up interconnect structures which are formed across each semiconductor die.
FIG. 1 shows a conventional FO-WLCSP 10 with semiconductor die 12 covered by encapsulant 14. A plurality of conductive pillars or vias 16 is formed through encapsulant 14 by mechanical drilling, laser drilling, or DRIE. A build-up interconnect structure 18 with bumps 19 is formed over the active surface of semiconductor die 12 and a first surface of encapsulant 14. An interconnect structure 20 is formed over a second surface of encapsulant 14, opposite the first surface of the encapsulant. The interconnect structure 20 is electrically connected to conductive vias 16. A semiconductor die 22 is mounted to interconnect structure 18 with bumps 24. An encapsulant 26 is deposited over semiconductor die 22 and interconnect structure 20. Semiconductor die 22 is electrically connected through bumps 24, interconnect structure 20, and conductive vias 16 to interconnect structure 18 and semiconductor die 12.
FIG. 2 shows another conventional FO-WLCSP 28 with a back surface of semiconductor die 30 mounted to a back surface of semiconductor die 32 using adhesive 33. The stacked semiconductor die 30 and 32 are covered by encapsulant 34. A plurality of conductive pillars or vias 35 and 36 is formed through encapsulant 34 by mechanical drilling, laser drilling, or DRIE. An interconnect structure 38 with bumps 39 is formed over the active surface of semiconductor die 32 and a first surface of encapsulant 34. The interconnect structure 38 is electrically connected to conductive vias 35. An interconnect structure 40 is formed over a second surface of encapsulant 34, opposite the first surface of the encapsulant. The interconnect structure 40 is electrically connected to conductive vias 35 and 36. Semiconductor die 30 is electrically connected through conductive vias 36, interconnect structure 40, and conductive vias 35 to interconnect structure 38 and semiconductor die 32.
FIG. 3 shows another conventional FO-WLCSP 41 with an active surface of semiconductor die 42 mounted to a back surface of semiconductor die 43 with an adhesive or insulating interposer 44. The stacked semiconductor die 42 and 43 are covered by encapsulant 45. A plurality of conductive pillars or vias 46 is formed through encapsulant 45 by mechanical drilling, laser drilling, or DRIE. An interconnect structure 48 with bumps 49 is formed over the active surface of semiconductor die 43 and a surface of encapsulant 45. The interconnect structure 48 is electrically connected to conductive vias 46. Semiconductor die 42 is electrically connected through conductive vias 46 to interconnect structure 48 and semiconductor die 43.
Each of the semiconductor package arrangements described in FIGS. 1-3 requires deep via formation and single or dual interconnect structures for routing signals between the stacked semiconductor die. The formation of deep vias by mechanical drilling, laser drilling, or DRIE is an expensive manufacturing step, which requires specialized equipment. In addition, the semiconductor package arrangements of FIGS. 1-3 often require fine top die placement, deeply embedded in encapsulant, which adds cost to the manufacturing process.